Hybrid System Level Power Modeling

. As the power dissipation becomes an important design constraint, especially in embedded systems, early and accurate power estimation is compulsory. The early power estimation dictates the design to meet the required specifications. In this paper, we describe efficient power modeling technique for embedded processors at higher level. We also present power models of two different processors using our methodology. Virtual Prototyping (VP) environment is used for benchmarking and power estimation using derived power models. Our methodology combines Functional Level Power Analysis (FLPA) with processor parameters, derived from processor counter information. Overall methodology applies Voltage and Frequency Scaling (VFS) along with FLPA and processor counters for the processor power modeling. We use a simulator to obtain such counters like total processor cycles and cache access cycles, which are highly dependent on algorithm. We have used an ARMTM embedded board for experimental power measurements. From real measured power data at different voltages, frequencies and cache access ratios we derive power models using regression for two embedded ARMTM processors. We used CarbonTM SoC Designer for VP of the system, and run different benchmark and integrated our power models to estimate processor power. Evaluation using four benchmark programs over different voltages and frequencies shows less than 9% and 4% errors for two processors. Our modeling techniques, as well as power models can be used for multicore processors.